Various types of solid state imaging devices/have been developed, which primarily include charge-coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensor devices, as well as hybrid image sensors that are based on a combination of CCD and CMOS image sensor designs. In general, CCD and CMOS solid state imaging sensors CCD image sensors operate based on the “photoelectric effect”, which occurs when silicon is exposed to light. In particular, CCD and CMOS image sensors include pixel arrays where each unit pixel includes a light receiving region including one or more photo detector elements (such as photodiodes) formed in an active silicon region of the pixel. When the light receiving region is exposed to light, photons in the visible and near-IR (infra red) light spectrums have sufficient energy to break covalent bonds in the silicon, thereby releasing electrons from the valence band into the conduction band. The amount of electrons generated is proportional to the light intensity. The photon-generated charges are accumulated by the photo detector elements in the pixel array, and then detected and processed to generate a digital image.
FIG. 1 is a schematic circuit diagram illustrating a unit pixel of a conventional CMOS image sensor device having a 4-transistor (4-T) active pixel sensor framework. In general, the exemplary unit pixel (10) comprises a PD (photo detector) element (or light receiving element), a transfer transistor TX, an FD (floating diffusion) region (or sense node), a reset transistor RX, an amplifier DX (or source follower amplifier), and a select transistor SX. The PD element may be a photodiode or a pinned photodiode, for example, which is formed in a light receiving region (or photosensitive region) of the pixel (10). The PD element is coupled/decoupled to/from the FD region by operation of the transfer transistor TX. The reset transistor RX has a gate electrode connected to an RS control signal line. The transfer transistor TX has a gate electrode connected to a TG control signal line. The select transistor SX has a gate electrode connected to an SEL control signal line and a source electrode connected to an output (column) line OUT. The transistors RX, TX, DX and SX are operated to perform functions such as resetting the pixel, transferring accumulated charges from the PD element to the FD region, and converting the accumulated charges in the FD region to a measurable voltage that is amplified and transferred to the output line OUT.
More specifically, the exemplary unit pixel (10) operates as follows. Initially, during an integration period (or charge collection period), the pixel (10) is illuminated with incident light and photo-generated charges are accumulated in a potential well (or charge accumulation region) of the PD element. After the integration period is complete, the reset transistor RX is activated by a reset control signal applied to the RS control signal line, to drain charge from the FD region and set the FD region to a reference potential (e.g., the FD region is charged to approximately the source voltage VDD less the threshold voltage of the reset transistor RX). After the reset operation, the transfer transistor TX is activated by a control signal applied to the TG control signal line to transfer the accumulated photo-generated charges from the PD element to the FD region. The amplifier transistor DX amplifies the voltage of the FD region and the amplified voltage is buffered/coupled to the column output line (26) via the select transistor SX, which is activated by a row select signal applied to the SEL control signal line.
Historically, analog CCD image sensors have dominated the market for solid-state imaging applications due to various advantages afforded by CCD image sensors, including superior dynamic range, low FPN (fixed pattern noise) and high sensitivity to light. Advances in CMOS technologies, however, have led to the development of improved CMOS image sensor designs, thereby allowing CMOS solid state image sensors to displace CCDs in various solid state imaging applications. Solid state CMOS image sensors afford various advantages including, for example, low cost fabrication, low power consumption with a single voltage power supply, system-on-chip integration, high-speed operation (e.g., capturing sequential images at high frame rates), highly-integrated pixel arrays, on-chip image processing systems, random access to unit pixels, etc. In contrast, CCD image sensor devices are expensive to fabricate, typically require 2, 3 or more supply voltages at different clock speeds with significantly higher power consumption, and do not allow random access to unit pixels.
Compared to solid state CCDs, however, conventional CMOS active pixel sensors have lower “fill factors”, which results in degraded performance (e.g., low sensitivity to incident light, low quantum efficiency, poor signal-to-noise ratio and limited dynamic range.). In general, the pixel “fill factor” (or aperture efficiency) refers to the ratio of the area of the light receiving region (or photosensitive region) of the pixel to the total area of the pixel. CMOS active pixel sensors have low “fill factors” due to the incorporation of the active circuits and associated interconnects in the unit pixels surrounding the designed photosensitive regions. The “fill factor” of a CMOS active pixel sensor is further explained with reference to FIG. 2, which schematically illustrates an exemplary layout pattern of a unit pixel (20).
As depicted in FIG. 2, the total surface area of the unit pixel (20) includes a defined photosensitive region (21) and a transistor region (22) that surrounds the photosensitive region (21). The photosensitive region (21) is the area of the pixel that is designed to capture incident light striking the pixel (20). A light receiving element (e.g., photodiode PD) is formed in the active silicon of the photosensitive region (21). The transistor region (22) is the pixel area in which the active components (e.g., amplifier, reset, and row select transistors) and BEOL (Back-End-Of-Line) interconnect structures are formed. For the most part, the transistor region (22) is essentially an “optically dead” region because most of the incident light on the transistor region (22) is absorbed or reflected by the active circuit components and interconnects within the region (22). Consequently, the photosensitive region (21) of the pixel (20), which is capable of absorbing photons to generate charge, is limited by the pixel area needed for the transistor region (22), resulting in a low fill factor. Various pixel designs include L-shaped photodiodes, rectangular shaped photodiodes and square-shaped photodiodes, which provide different “fill factors”.
Although the transistor region (22) is, for the most part, an “optically dead” region of the pixel (20), some light incident can be absorbed by the underlying substrate of the transistor region (22) resulting in generation of photo-generated charges. These photo-generated charges can be collected in the potential well of the PD element. In this regard, the “designed” fill factor of the active pixel (which is based on the actual exposed area (aperture) of the photosensitive region (21)) differs from an “effective” fill factor because the transistor region (22) of the pixel can also contribute to charges collected in by the PD element. Moreover, some of the photo-generated charges in the transistor region (22) can be captured by the junctions (e.g., FD region) or potential wells of active components in the transistor region (22), or can diffuse to, and be collected in, PD elements of neighboring pixels. Consequently, the generation of photo charges in the transistor region (22) can result in noise and cause non-uniform pixel response across the pixel array.
In some conventional active pixel designs, pixel response non-uniformity is mitigated by use of a separate metal light shield layer formed over the pixel array, wherein the light shield layer operates to shield incident light from pixel transistor regions, but comprises apertures aligned to the photosensitive regions to allow incident light to reach the photosensitive regions of the pixel. Essentially, the light shield layer operates to separate the pixel response of the defined photosensitive region from that of the transistor regions and, thus, achieve a more uniform pixel response across the pixel array. The use of additional light shields, however, result in reduced pixel fill factor and lower Quantum Efficiency (QE) performance (and thus, degraded performance), and place design constraints for constructing active pixels sensors, as will be explained with reference to FIG. 3.
FIG. 3 is a schematic side view of a unit pixel of a conventional CMOS active pixel sensor having a separate light shield layer. In particular, FIG. 3 illustrates a portion of a unit pixel formed in an active region of a semiconductor substrate (30) defined by an isolation layer (31). A photodiode element PD and diffusion regions (32) and (33) are formed in the active silicon region of the pixel. A stacked structure (34) is formed over the substrate (30). The stacked layers (34) include a plurality of gate electrodes (e.g., transfer and reset transistors Tx and Rx) and alternating layers of transparent dielectric layers and opaque metal layers that form the BEOL metallization interconnects. A upper metal layer is formed to operate as a light shield (34a) having a defined opening (aperture) (34b) of width, w, which is aligned to the PD element in the substrate (30). Some incident light on the pixel surface is reflected/blocked by the metal shield (34a) and some incident light enters through the aperture (34b) and passes through a tunnel region (34c) of the stacked layers (34) (which is devoid of metal lines of the BOEL structure) and is absorbed by the PD element.
Although the light shield (34a) can increase uniformity of pixel-to-pixel response, the use of the separate light shield layer (34a) lowers the pixel sensitivity. Indeed, the use of the additional light shield layer (34a) results in an increase in the height h of the stacked layers (34), and thus increases the aspect ratio of the tunnel height to the aperture width (i.e., the ratio of h/w). As the aspect ratio increases, the amount of incident light that can pass through the aperture (34b) to the PD element decreases as a result in the limited angle of incidence, which results in lower pixel sensitivity and lower QE. As CMOS technology scales to smaller feature sizes, smaller size pixels and light shield apertures can be formed to increase integration density. On a practical level, however, the size of active pixels sensors will be limited despite smaller available design rules due to a required level of pixel sensitivity needed for effective operation. Indeed, as the pixels with separate light shields are constructed with smaller design rules, the aspect ratio of the tunnel height h to the aperture width w increases, which results in decreased pixel sensitivity. Thus, to enable smaller design rules, it is desirable to limit the height h of the stacked layers (34) above the substrate (30), while using effective light shielding to minimize variation of pixel-to-pixel sensitivity across a pixel array.